A method for timing closure in supply voltage scaled CMOS digital circuits with dual-Vth devices
Power has become a dominant problem of chip designers nowadays. Thus, scaling down the supply voltage beyond the nominal has been a popular solution to significantly decrease the power consumptions of circuits. However, the lack of standard cell library characterizations at lower supply voltages pre...
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| Format: | Thesis |
| Language: | English |
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Quezon City
College of Engineering, University of the Philippines Diliman
2013
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