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  1. 1

    Implementation of local voltage dithering on the ARM7 microprocessor in a 90nm CMOS process by Cada, Mark Angelo A.

    Published 2011
    Thesis

    Implementation of local voltage dithering on the ARM7 microprocessor in a 90nm CMOS process
  2. 2

    A USB 2.0 controller for an ARM7TDM-S processor implemented in FPGA by Difuntorum, John Keithley L.

    Published 2011
    Thesis

    A USB 2.0 controller for an ARM7TDM-S processor implemented in FPGA
  3. 3

    SCARM a memory simulator with a compiler-assembler for the 32-bit ARM7 microprocessor by Barahan, Nicole John Antonio

    Published 2011
    Thesis

    SCARM a memory simulator with a compiler-assembler for the 32-bit ARM7 microprocessor
  4. 4

    Design and implementation of a 32-Bit dual core capable DLX microprocessor with single-level cache by Dioquino, Darryl Aldrin M.

    Published 2007
    Thesis

    Design and implementation of a 32-Bit dual core capable DLX microprocessor with single-level cache
  5. 5

    C compiler back end for the 32-bit dual core capable DLX microprocessor by Ostrea, Allan Michael M.

    Published 2007
    Thesis

    C compiler back end for the 32-bit dual core capable DLX microprocessor
  6. 6

    A study of floating-point architectures for pipelined RISC processors by Reyes, Joy Alinda P.

    Published 2005
    Thesis

    A study of floating-point architectures for pipelined RISC processors
  7. 7

    A study of selective power-down techniques for low-power RISC microprocessor design by Khalid, Sihawi Abdulhamid

    Published 2004
    Thesis

    A study of selective power-down techniques for low-power RISC microprocessor design
  8. 8

    A study of selective power-down optimization techniques for low-power integrated RISC execution unit design by Bantug, Arianne Contemprato

    Published 2003
    Thesis

    A study of selective power-down optimization techniques for low-power integrated RISC execution unit design
  9. 9

    A study of data transfer mechanisms in a RISC microprocessor augmented with a tightly coupled reconfigurable processing element (RPE) by Alarcon, Louis Poblete

    Published 2002
    Thesis

    A study of data transfer mechanisms in a RISC microprocessor augmented with a tightly coupled reconfigurable processing element (RPE)
  10. 10

    32-bit pipelined RISC microprocessor by Lee, Leonard

    Published in Philippine Engineering Journal (2000)
    Article

    32-bit pipelined RISC microprocessor

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